[Remote] PCIe ASIC Design Engineer

Note: The job is a remote job and is open to candidates in USA. Cornelis Networks is building the future of AI and HPC networking with an AI-first approach to silicon and software development. They are seeking a Senior ASIC Design Engineer to lead the design and integration of PCIe controllers into next-generation SoCs, focusing on performance optimization and compliance with PCIe specifications.

Responsibilities

• Own end-to-end integration of PCIe IP into complex ASIC designs
• Collaborate with IP vendors, architecture, verification, physical design, and software teams to deliver robust PCIe subsystems
• Drive performance optimization efforts across the PCIe stack, from PHY tuning to DMA/transaction layer efficiency
• Contribute to system architecture and microarchitecture discussions with a focus on IO and interconnect scalability
• Lead silicon bring-up and validation of PCIe links in the lab; work closely with board and firmware teams
• Debug functional and performance issues at RTL, gate-level, and silicon
• Ensure compliance with PCIe specifications and participate in interoperability testing where needed
• Provide mentorship to junior engineers and help define PCIe subsystem development best practices
• Good understanding of high-bandwidth, low-latency connectivity for high-performance compute platforms

Skills

• BS/MS in Electrical Engineering, Computer Engineering, or related field
• 10+ years of industry experience in ASIC/SoC design with a focus on PCIe controller integration
• Proven experience in silicon bring-up and debug of high-speed interfaces
• Solid understanding of PCIe protocol stack (PHY, MAC, TLP, DLL), configuration space, and link training
• Hands-on experience with PCIe verification environments, performance tuning, and power-aware design
• Familiarity with PCIe compliance testing, simulation tools (e.g., VCS, Questa), and lab equipment (e.g., protocol analyzers, oscilloscopes)
• Strong scripting (Python, Perl, TCL) and debugging skills
• Strong verbal and written communication skills
• Experience with PCIe Gen5/Gen6 and advanced retimer or switch solutions
• Exposure to CXL, CCIX, or other cache-coherent interconnects
• Background in data center or AI/ML accelerator architectures
• Experience with emulation and prototyping platforms (e.g., ZeBu, Palladium, HAPS) for PCIe subsystem validation

Benefits

• Equity
• Cash
• Incentives
• Health and retirement benefits
• Performance-based incentives, including an annual bonus or sales incentives
• Medical, dental, and vision coverage
• Disability and life insurance
• Dependent care flexible spending account
• Accidental injury insurance
• Pet insurance
• Generous paid holidays
• 401(k) with company match
• Open Time Off (OTO) for regular full-time exempt employees
• Sick time
• Bonding leave
• Pregnancy disability leave

Company Overview